This application is related to Japanese application No. 2001-137475 filed on May 8, 2001, whose priority is claimed under 35 USC xc2xa7 119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device whose gate oxide film is less damaged by a plasma charge during formation of an interlayer dielectric film in processes for manufacturing a semiconductor, and a method for manufacturing the semiconductor device.
2. Description of Related Art
Among the processes for manufacturing a semiconductor, there are many in which plasma is used.
FIGS. 6 (a) and (b) illustrates a gate electrode 21 of a transistor and a wiring 22 connected thereto which constitute a typical semiconductor device. In manufacture of such a semiconductor device, there are many processes in which a plasma is used at the stages of forming the wiring 22 and thereafter. As those processes, there may be mentioned processes using a plasma-etching for patterning the wiring 22, plasma-ashing for removing a resist film, a plasma CVD method for forming an interlayer dielectric film, a plasma-etching for forming a via hole in the interlayer dielectric film and the like.
In plasma, there are ions and electrons produced by ionization. If a semiconductor substrate 20 shown in FIGS. 6(a) and (b) is exposed to a plasma in which a balance in ions and electrons between positive and negative charges is destroyed, electrons enter from a surface of the wiring 22 exposed to the plasma, and flow into the semiconductor substrate 20 via the gate electrode 21 and a gate oxide film 23.
Then, if a large amount of current flows in the resulting transistor or the like, damage is caused to the gate oxide film 23, leading to dielectric breakdown, reduction in long-term reliability or the like. Also, yield in LSIs is lowered. Such damage, which is referred to as plasma damage because it is electrical damage caused by a plasma, is becoming an increasingly severe problem since it causes a significant deterioration or the like as a device is more miniaturized and the thickness of a gate oxide film is more reduced.
Typically, a wiring formed of a conductive film such as a metal film and exposed to a plasma serves an antenna. Conventionally, the antenna is often discussed in terms of the areas of side walls of a wiring 25, because the plasma damage is outstanding mainly in an etching process in which the wiring 25 is covered with a resist film 26. However, recently, a high density plasma (HDP) CVD method is used for formation of an interlayer dielectric film positioning between wirings, and it becomes necessary to define an entire surface area of the wiring as an antenna.
A ratio of the entire surface area of the wiring connected to a gate electrode to the surface area of the gate oxide film is defined as xe2x80x9cantenna ratioxe2x80x9d to be used as quantitative index of a degree of the plasma damage. Accordingly, if a wiring is of a large pattern like pad, the antenna ratio is generally great which results in a serious plasma damage to the gate insulating film or the like.
A measure against the plasma damage is proposed in, for example, Japanese Unexamined Patent Publication No. Hei 11(1999)-40564.
A semiconductor device described therein is constructed as follows. A first wiring 34a is formed above a gate electrode 31 with a contact 33 interposed therebetween. The contact 33 is formed in an interlayer dielectric film 32. Further, there is formed another first wiring 34b which is not connected to the gate electrode 31. Also, a second wiring 37 is formed above the first wirings 34a and 34b via contacts 36a and 36b interposed between the second wiring 37 and the first wiring 34a and between the second wiring 37 and the other first wiring 34b, respectively, as shown in FIGS. 8 (a) and (b). The via contacts 36a and 36b are formed in an interlayer dielectric film 35.
In the semiconductor device shown in FIGS. 8(a) and (b), because only the first wiring 34a which is connected to the gate electrode 31 serves as an antenna, the antenna ratio can be small. Accordingly, even if the other first wiring 34b is of a large pattern such as a bonding pad, the plasma damage to the gate oxide film 38 is minimized.
However, in the semiconductor device shown in FIGS. 8(a) and (b), because an additional wiring layer is provided, throughput is lowered and cost is increased. Further, yield may possibly be reduced by an increase in the number of processes.
The present invention has been made in view of the above circumstances and an object thereof is to provide a semiconductor device in which the plasma damage is reduced only by a change of the configuration of a wiring and without an increase in the number of masking processes or wiring-formation processes, and a method for manufacturing the semiconductor.
The present invention provides a semiconductor device comprising: a MOS transistor having a gate electrode formed on a semiconductor substrate, a wiring connected to the gate electrode via a first insulating film, an antenna pattern for reducing a plasma damage in the form of lines/spaces connected to the wiring, and a second insulating film formed on the wiring and the antenna pattern.
Also, the present invention provides a method for manufacturing a semiconductor device comprising the steps of: forming a MOS transistor on a semiconductor substrate, forming a wiring and an antenna pattern for reducing a plasma damage in the form of lines/spaces connected to a gate electrode constituting the MOS transistor via a first insulating film on the MOS transistor, and forming a second insulating film on the wiring and the antenna pattern by a CVD method while applying bias voltage to the semiconductor substrate.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.